The present invention generally relates to semiconductor packages and more particularly to power semiconductor packages and methods of making power semiconductor packages.
Optimizing the operational performance of power semiconductor packages requires satisfaction of several constraints. The constraints include acceptable power density, parasitics, reliability and cost of manufacture. Power density is related to heat dissipation of the package. As a result, obtaining desired power density often requires efficient cooling of the package. One manner in which to achieve cooling of the package is by exposing thermally conductive features, such as metal and silicon, of the active components of the package to an ambient environment. It is typically desired to configure the package to provide mechanical protection to the silicon features.
Elimination of wire bonds facilitates obtaining acceptable parasitics (e.g., parasitic resistance and inductance). To that end, interconnection of the active components is often facilitated by clip bonding, chip-only ball grid array with solder balls/bumps. The drawback of clip bonding is that the top exposure area is limited and a traditional mold process is required for package integrity. The drawback of chip-only ball grid array is that the connection to certain active components, such as the drain of a bottom-drain vertical MOSFET, is problematic. The mechanical integrity of the ball grid array may become compromised when operating at the upper power limits of the package. In addition, the semiconductor chip may be exposed to physical damage in such a configuration. The process of mounting a semiconductor chip, or a package with multiple chips may also experience stresses from the different coefficients of thermal expansion.
Cost of manufacture may be controlled by minimizing the amount of materials employed to fabricate the same. This may be achieved by obtaining, as close as possible, the ratio of the size of the package to the size of the active element to be 1:1. Also, the miniaturization of parts is an ongoing goal in the field of electronics. Reducing the complexity of the process by which to fabricate the package may also reduce cost.
Reliability may be provided by ensuring the mechanical strength of the package. To that end, it would be desired to provide physical protection to the semiconductor silicon of the active elements, while improving the robustness of the package.
A need exists, therefore, to provide power semiconductor packages having desired operational characteristics.